First post, by pentiumspeed
This board is a beauty to behold but I have questions.
This website have a manual for this board: Please examine photo and this manual.
Manual:
https://theretroweb.com/motherboard/manual/s7 … 84171195803.pdf
Look at photo in this link:
https://theretroweb.com/motherboards/s/ami-atlas-pci-ii-s727
This board supports up to 1MB either async ( async aren't not soldered along with missing pair of 74F373 and missing SMD resistor that pulls down the Output Enable Input (Active LOW) to both 74F373 ICs pin 1.)
Supports 32K x 8, 64K x 8 or 128k x 8 for 256K, 512K or 1MB. There is one 3 pin jumper not soldered at J30 for enable or disable async cache which also works with J16 which selects either async or sync. (installed with a jumper). The pair of jumpers J26 and J28 sets the cache size 256K, 512k or 1MB for either types of cache.
Or sync cache up to 1MB using Intel COAST version 1.0 but I could not find the PDF for designing the COAST version 1.0, anyone could help here?
Finally, U30 is a 32K x 8 soldered async for tag. But there is another U29 tag IC not occupied.
Another question. Why did this board have soldered U30 tag ram even the COAST module already have tag ram included even this board does have COAST slot already.
I have a COAST module with 512K and tag ram but have two more spaces for another 512K to make 1MB cache using four 64K x 32bit chips module and second tag ram solder pads is also there. This why I need the datasheet on designing COAST module.
Great Northern aka Canada.