First post, by Paul_V
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Hi,
I'm writing this as a last resort in attempt to get some help downclocking AMD Geode LX800 CPU.
I've been tickering with it for quite a while and seem to hit a brick wall.
As the time goes by, my gathered knowledge of it starts to fade and would hate to just quit now without at least sharing some findings.
Test subject:
For testing, I've been using a motherboard from Fujitsu Siemens Futro thin client: TR2350
It comes with Insyde XpressROM BIOS, which is basically useless for retro rig use.
I managed to find compatible BIOSes from AMI and AWARD (even Insyde too, but it's a PITA to mod), which even allow to change CPU\GeodeLink multipliers (1 to 32)
My goal:
Devise a way to downclock this CPU as low as possible, using it's multiplier settings, as it would make it very versatile speed wise.
A couple of findings so far:
1) A big collection of dev board firmware from AMI, one of which fit TR2350 perfectly. Which is expected, because the design is almost similar to AMD development board.
https://www.ami.com/resources_with_downloads/amd/
2) You can change the multiplier on the fly by editing MSR registers to some extent. They are listed in LX800 Databook
3) Native 1600x1200 under DOS (I have no way of determining whether it is 320x200 or 740x400 or any other resolution that is scaled to 1600x1200 though)
4) It can run either 33 or 66Mhz PCI bus, has internal PLL divider (you can get same frequencies with ether lower multiplier without divider, or do PLL/2 and higher mult. number)
5) RAM bus speed is dependent on Geodelink multiplier.
6) Databook (datasheet) links
https://www.amd.com/content/dam/amd/en/docume … LX_databook.pdf
My problem:
Lowest CPU stable speed I got is 166Mhz (33x5). Lowest unstable is 133Mhz (33x4)
By trial end error, I'm pretty sure now that LX800 CPU clock:
a) Cannot be lower than PCI bus clock (which is 33 or 66Mhz, depending on hardare straps etc).
b) Cannot be lower than DDR base clock. (which is the source of my problem)
DDR introduced so-called Delay-Locked-Loop circuit (or DLL in short) to make it stable at intended clock speed.
But there is a catch - DLL stops working at lower speeds thus, preventing DDR init at speeds lower than 125Mhz (according to JEDEC specs)
So, without disabling DLL, the lowest DDR speed is 33x4 (stable) or 33x3 (unstable, basically unusable)
Probable solution (And that is where it gets painfull)
DLL can be disabled without causing stability issues, provided the clock speed of DDR is relatively low.
All the info about disabling DLL is mentioned in the datasheets.
Except there's one small detail: DLL state is programmed by BIOS during hadrware initialization.
Which means I have to basically disassemble the bootblock, find memory init routine and disable DLL (easy peasy, huh?)
And that is way above my current programming and BIOS skill levels.
Maybe there's a compiled menu option in the code, which is not exposed. (because I've checked all BIOSes for hidden options to no avail)
There were some promising leads to extract all possible compiled AMIBIOS8 options using AMISCE, but unfortunately, my BIOS version is not compatible.
So here I am. Basically crying out loud for any experienced BIOS modders\programmers help or advice )
Maybe someone can point to an alternative solution to disable DLL? Low level BIOS programming is not something you can do on every LX800 board you find.
Both AWARD and AMI compatible BIOSes are in the attachment.