Here are the cache mods:
The 486SXL and to a lesser extent the 486DLC require some modifications to get the full benefit of the cache although they will still be substantially better than the original 386 even without them. There are two signals that need to be sent to the processor:
1. A20 Gate. This is used to signal when the A20 gate is active causing wraparound of the 1st 1MB of memory to exactly simulate the behaviour of the original 8088
2. Cache flush on DMA. This is used to flush the cache whenever there is a DMA operation by other hardware. Unless you install some expansion card like a SCSI controller, the only time this happens is when the floppy drive is read.
The A20 Gate mod is a single wire but the cache flush requires a 74HC00 logic gate IC to generate the signal.
This diagram shows the pinouts of the CPU and the 82385 Cache Controller (both viewed from pin side) together with the flush circuit:
The attachment Flushmod.jpg is no longer available
And this is an overview of the mods on the underside of the motherboard (yellow wires are the flush mod and blue wire is the A20 mod):
The attachment overview.jpg is no longer available
The A20 mod is a wire from Pin 8 of IC 43 to pin F13 (A20M#) of the 486 CPU (blue wire)
The attachment a20-cpucc.jpg is no longer available
The cache mod is made as follows:
Wire from The ISA MEMW# signal to pins 1 and 2 of the 74HC00. (The MEMW# signal can be found on the rear end of R517)
Connect pins 3 and 4 of the 74HC00 together
Wire from pin M11 (BHLDA) of the 82385 cache controller to pin 5 of the 74HC00
Wire from pin E13 (FLUSH#) of the 486 CPU to pin 6 of the 74HC00
Mounting the 74HC00
I used a surface mount 74HC00 and mounted it face down on the PCB adjacent to C29 which is a decoupling capacitor with +5v and 0V available.
I connected pin 7 to the front side of C29 (0v) and used a bare wire to connect the rear side of C29 (+5v) to pins 9,10,12,13 & 14.
Pins 8 and 11 which are outputs have been cut off close to the body of the chip and do not make contact with the wire.
Warning: The position and orientation of R517 and C29 are based on the PCB in my systems, later PCB issues may have moved them.
I have added pin numbers on the 74HC00 in the photo below: (numbering is reversed from normal as the IC is face down)
The attachment chip-memw.jpg is no longer available
These mods require my patched BIOS to work (see front page).
The A20 mod is auto detected by the patch code but the cache mod can't be detected unless there is a floppy in the drive so the patched BIOS assumes it has been made if it detects the A20 mod and configures the CPU accordingly.
Testing the mods:
If you get the A20 mod wrong, the BIOS will not configure the CPU for either mod.
If you get the A20 mod right but the cache flush mod wrong, the T5200 will probably hang when trying to boot a floppy.
I'll update this post with some more testing details including some test software soon.