If anything, GF1 is a close relative of some ICS chips like the WaveFront stuff. Very similar register layouts and functions (and GF1 is manufactuerd by ICS 🤣)
The Otto seems to work only conceptually similar way but not actually share much in common from what I have seen form available documentation.

The silicon is night and day, completely different design practices.

Tiido wrote on 2024-06-23, 08:12:

If anything, GF1 is a close relative of some ICS chips like the WaveFront stuff. Very similar register layouts and functions (and GF1 is manufactuerd by ICS 🤣)
The Otto seems to work only conceptually similar way but not actually share much in common from what I have seen form available documentation.

The silicon is night and day, completely different design practices.

Okay well that clears stuff up , thanks 😆

Also speaking of which cause its related it seems that Nukeykt is working on a fpga GUS?

https://github.com/nukeykt/LPC-GUS

He's nearly done tracing it.

Or maybe has at this point.

That chip I donated for decapping is put to good use ~

Tiido wrote on 2024-06-23, 09:34:

That chip I donated for decapping is put to good use ~

Yerp it was sacrificed for a greater cause.

What's the significance of the LPC bus though , its some sort of a connection standard by the looks of it?
Is it just for testing , or an alternative way of connecting devices?

LPC is basically compactified ISA that you can find on modern(ish) boards, normally used by integrated peripherals like SupeIO chip. That way he can do dev and testing on the dev machine and not need to mess back and forth with an old thing as part of dev and testing.

Tiido wrote on 2024-06-23, 10:03:

LPC is basically compactified ISA that you can find on modern(ish) boards, normally used by integrated peripherals like SupeIO chip. That way he can do dev and testing on the dev machine and not need to mess back and forth with an old thing as part of dev and testing.

Ahk.

AppleSauce wrote on 2024-06-23, 10:08:

Tiido wrote on 2024-06-23, 10:03:

LPC is basically compactified ISA that you can find on modern(ish) boards, normally used by integrated peripherals like SupeIO chip. That way he can do dev and testing on the dev machine and not need to mess back and forth with an old thing as part of dev and testing.

Ahk.

LPC means "low pin count", and has been introduced by Intel with the 800 series of chipsets. According to the Intel specification of LPC, a typical LPC 8-bit super I/O device just uses 6 new "LPC" signals instead of 36 signals on the ISA bus, saving 30 pins (and 30 traces on the mainboard). This comparison might be slightly skewed, as the bus clock signal is not in that list (there is a bus clock on ISA and a bus clock on LPC, so the bus clock is not considered a "new" signal on the LPC or a "removed" signal. On the other hand, ISA targets can generally ignore the bus clock, but the bus clock is essential for LPC targets, so take the number "30" with some grain of salt. On the other hand, the number of traces removed from the mainboard is even larger, as there might be 16-bit memory devices on the LPC bus which would require 4 extra address bits, 8 extra data bits and a 16-bit negotiation signal. All-in-all, I expect the number of signals the south bridge outputs for LPC being around 50 lower than for ISA. Going to LPC allows less pins on the south bridge, less pins on LPC devices and less traces on the mainboard, at the expense of not being able to easily provide ISA slots on the board (440BX boards use classic ISA at the south bridge and (usually) provide ISA slots; 810 and 815 boards use LPC and (usually) do not provide ISA slots. See dISAppointment - LPC to ISA adapter - ISA on modern motherboards for a thread about an adapter that translates LPC to ISA.

AppleSauce wrote on 2024-06-23, 07:36:

But supposedly the story goes that the GF1 chip on the gravis is based on the OTTO chip

on Wikipedia since 2015 added by anonymous ip
https://en.wikipedia.org/w/index.php?title=En … oldid=645285307

rasz_pl wrote on 2024-06-23, 13:17:

AppleSauce wrote on 2024-06-23, 07:36:

But supposedly the story goes that the GF1 chip on the gravis is based on the OTTO chip

on Wikipedia since 2015 added by anonymous ip
https://en.wikipedia.org/w/index.php?title=En … oldid=645285307

Hm very mysterious , they made a bunch of other edits around the same time

That said there is a google groups post from 1993 discussing the origin of the card.

https://groups.google.com/g/comp.sys.ibm.pc.s … /m/u-byYJBcUF4J

Seems Paul Travers kinda confirms what Tiido said , that ICS did their own spin on things , though apparently Forte did license some kind of ensoniq technology?

Actually, isn't the GF1 closer to Commodore's PAULA than anything done by Ensoniq?

Paula is primitive by comparison, there's nothing similar between it and GF1.

As I understand, there are three similar wavetable chips: Ensoniq OTTO, ICS Wavefront and GF1 having similar architecture. They allow playing UP to 32 samples simultaneously decreasing the frequency after some amount of voices (GF1 after 14, OTTO after 24) from 44100 kHz to 20kHz. Pitch height is changed somehow - via changing playback speed? Via interpolating the sample data?

There are no effects. All three have loop points, OTTO and Wavefront have hardware envelopes - what about GF1? Seems like that's it? And seems like GF1 is the least capable of them, it's main benefit is using the RAM instead of ROM. Am I right?

Pitch is changed by stepping through the sample faster or slower, by adjusting the increment value on phase accumulators which are updated once per output sample. There is only one sample memory access per channel per sample period, with some interpolation and possible filtering on top to smoothen out the sound a bit (same ideas as image scaling, just 1D and not 2D).

When too many channels need to be played, sample frequency is decreased because there aren't enough master clocks left to maintain sample rate. If you increase master clock you make memory timings faster in the process and that will be a problem for the sample memory which likely cannot meet the timings anymore. Wavefront chips run at a faster master clock and don't have the problem of running out of cycles, but it needs comparatively faster memory to do its job at a given sample rate.

GF1 has envelopes, or at least it gives you start+end+speed parameters, which then need to be manually updated to get different sections of a typical ADSR envelope happen. It can produce an IRQ when end is reached and then the IRQ handler can prepare the next stage of the envelope etc.

RAM vs ROM is only a logical distinction, although GF1 does lack any ROM support since it only has a DRAM interface (but there's nothing stopping you from demuxing the address bus and using a ROM chip if you wanted to, just no existing game will function in such a setup).

Tiido wrote on 2024-12-24, 06:59:

Pitch is changed by stepping through the sample faster or slower, by adjusting the increment value on phase accumulators which a […]
Show full quote

Pitch is changed by stepping through the sample faster or slower, by adjusting the increment value on phase accumulators which are updated once per output sample. There is only one sample memory access per channel per sample period, with some interpolation and possible filtering on top to smoothen out the sound a bit (same ideas as image scaling, just 1D and not 2D).

When too many channels need to be played, sample frequency is decreased because there aren't enough master clocks left to maintain sample rate. If you increase master clock you make memory timings faster in the process and that will be a problem for the sample memory which likely cannot meet the timings anymore. Wavefront chips run at a faster master clock and don't have the problem of running out of cycles, but it needs comparatively faster memory to do its job at a given sample rate.

GF1 has envelopes, or at least it gives you start+end+speed parameters, which then need to be manually updated to get different sections of a typical ADSR envelope happen. It can produce an IRQ when end is reached and then the IRQ handler can prepare the next stage of the envelope etc.

RAM vs ROM is only a logical distinction, although GF1 does lack any ROM support since it only has a DRAM interface (but there's nothing stopping you from demuxing the address bus and using a ROM chip if you wanted to, just no existing game will function in such a setup).

What you wrote sort of made me wonder if a switchable (that could be disabled for backward compatibility) MMU could, at least theoretically have been added between a GF1 and its memory to handle transparent (to the GF1) address remapping of a larger memory space into the GF1's 1MB address space . I suspect this would have been impractical (impossible?) to manage and/or subject to too high latency .

It is definitely possible to do such a thing externally, although I am not all that sure about timing margins. GF1 is made to function with 80ns DRAMs, with the extra logic it can need 70 or 60ns ones.

That's interesting. And what about 68K CPU, which of these three chips contain that core?

rkurbatov wrote on 2024-12-24, 15:08:

That's interesting. And what about 68K CPU, which of these three chips contain that core?

None do. The Ensoniq Soundscape had a 68K CPU as separate chip, and the Sequoia (IIRC) chip as "system controller" connecting the CPU to the ROM, RAM, OTTO and ISA bus.