Last incarnations (like Goldstar Prime2, Prime2c) are 1 chip solution (maybe except for LS245 buffers for IDE).
I doubt that such a simple design could require 4-layer PCB.

pentiumspeed wrote on 2022-07-08, 00:44:

Reason for choosing one so I can reproduce it in 4 or 6 layer PCB instead of two layers and much better routing

What would be the purpose considering all ISA IDE "controllers" are just fancy address decoders. The real IDE controller is on the drive. I encourage you to do a deep dive into IDE history by reading articles at https://www.os2museum.com/wp/category/ide/
It all started as https://en.wikipedia.org/wiki/ST506/ST412 ISA controllers + separate dumb drives. There were even steps between, one side IDE the other interfacing ST506 drives https://www.os2museum.com/wp/learn-something- … ry-day-part-ii/
Then Conner finally integrated it into one unit.

TLDR: ISA IDE controller is not a controller at all. IDE disk is a fancy ISA expansion card using custom connector and being mapped to specific fixed IO address space.

Indeed. Most controllers are just adaptors. However, there are still some are a bit smarter (a BIOS extension to handle geometry translation). And even some that are actually HBAs, like cached controllers, like this one:

Thank you and I'll read them up.

I'm curious how adjustable address how it works with jumpers as I'm having hard time understanding how ISA bus from card's view stuff does.

Cheers,

Goldstars are popular, due to being easy to recognise, but they tend to die in weird ways. Winbond used to be looked down on as the lowest of the low and were plentiful, but aside from allegations of slowness, seem to get the job done, sorta comparable to Realtek ethernet. Also the winbond chips seemed to get a life extension as providing legacy I/O on boards to the late 370 era. I think some of those still have their entire functionality intact even if they only use half of it for motherboard I/O

http://www.alexandrugroza.ro/microelectronics … face/index.html
whole ISA IDE interface is 2x 245 buffer + 244/128 address decoding + one PAL used for convenience

another one, with 8bit bus conversion https://www.retrobrewcomputers.org/lib/exe/fe … -ide_v2-sch.pdf

quite hardcore cost optimized IDE controller, no buffering on 8 upper bits. Only 3 chips, 2 doing address decoding and 1x 245 buffering lower 8bits

extreme hardcore, down to one PAL doing address decoding + 245 buffer

we are reaching ridiculous extreme, no data lines buffering at all 😀. Note this isnt strictly super bad, IDE drive will have buffers onboard anyway.

more at https://computer-retro.de/Multi-IO.html

Had bad experience with boards using PAL chips in past starting with early 286 and 386 board and one ATI wonder 8 bit card blew their 6 PAL chips they actually browned the board too!

Is there documentation on IDE aka PATA interface all TTL, no hint of any PAL?

Cheers,

mpe wrote:

However, there are still some are a bit smarter (a BIOS extension to handle geometry translation). And even some that are actually HBAs, like cached controllers, like this one:

Would be ironic to install such card into 286.

pentiumspeed wrote on 2022-07-08, 19:32:

Had bad experience with boards using PAL chips in past starting with early 286 and 386 board and one ATI wonder 8 bit card blew their 6 PAL chips they actually browned the board too!

? PALs/GALs were used in the hundreds of millions in everything since late seventies

pentiumspeed wrote on 2022-07-08, 19:32:

Is there documentation on IDE aka PATA interface all TTL, no hint of any PAL?

I think in the first link its only used to enable two IDE channels buffer arbitration and D7 since it didnt fit in 245? remove one channel and rework buffering (can probably remove as evidenced by those extremely barebones controllers I linked) and you can drop the PAL. All you need is decoding two address ranges 0x1F0-0x1F7 and 0x3F6 https://wiki.osdev.org/ATA_PIO_Mode
also https://www.pjrc.com/tech/8051/ide/wesley.html for microcontroller IDE interfacing