Looks like i got it. In P1 all CPU units designed to work through L1 cache. Once L1 cache disabled all memory read/writes results in cache lookup with guarantied cache miss - only after that CPU can issue 1 memory IO 😀
While 386 just reads from memory - with no lookup overhead.

PS. I wonder if P1 initiates cache line fill for each IO with disabled L1 cache 😁

gerwin wrote:

After that I also tried it with one of my Pentium MMX processors, 200 or 233MHz (P55C): The TR12 switches no longer had any effect.

I have to correct myself here. I just tried out all my Pentium MMX processors with the SetMul TR12 options, while benching them with SpeedSys before and after.

Pentium MMX 233 SL27S 5.4.3
Pentium MMX 200 SL26J 5.4.4
Pentium MMX 200 SL27J 5.4.3
Pentium MMX 166 SL27H 5.4.3
Pentium MMX 166 SY059 5.4.4
Pentium MMX 166 SL239 5.4.4 (Ceramic one)

They all slow down considerably with all five of the TR12 features disabled! From 90..157 SpeedSys points to 24..27 points. 😮

clueless1 wrote:

Sadly, in retesting my Pentium 120 cpu with the test registers, I found DCD and CCD (data and code cache) have no effect. These two switches are what allow my POD 200MMX to get into 486 levels of performance. VPD and BPD do work, which allow smaller performance drops into P90 and P100 ranges.

I ran the test with the same six processors, but this time using only the parameters 'CCD DCD'. All processors slowed down from 90..157 SpeedSys points to 32..30 points.

You can find my results in https://docs.google.com/spreadsheets/d/1uKhCI … dit?usp=sharing from the Cache Disable Benchmark thread. I did every possible combo on my MMX233 @ 233 and 133 speeds -- there are a lot. This chip provides the best/smoothest 386/486 scaling on a SS7 board, I believe.

Great work! Just what I was curious about. That is indeed a lot of different speeds. I actually knew you had submitted such tests, but did not fully realise it already proved that TR12 options are present on the ordinary 233 MMX. I am too busy with other things I guess.
(I suppose there can be even more results with the 233 MMX by throwing in the 100MHz bus of Super Socket 7, and the 2.5x and 3.0x multiplier option.)

infiniteclouds wrote:

You can find my results in https://docs.google.com/spreadsheets/d/1uKhCI … dit?usp=sharing from the Cache Disable Benchmark thread. I did every possible combo on my MMX233 @ 233 and 133 speeds -- there are a lot. This chip provides the best/smoothest 386/486 scaling on a SS7 board, I believe.

That's my observation, as well.

Being able to toggle between 233 and 100 would be even more versatile.

Yeah unfortunately my SS7 board doesn't do 50 FSB. I don't notice L2 motherboard cache on your graph? It did affect speeds on my Pentium MMX -- but it had to be disabled in BIOS, not using the L2D command.

I'm working on bench-marking the scaling of my current Slot 1 build but it is going to take a while. There are less switches and no L2 cache but still 5 switches that yield different speeds (ICD, BPD, ICD+BPD, L1D and L1D+BPD), combined with 7 different FSB speeds to choose from and a whopping 16 different multipliers - it's incredible. Even when a certain multiplier/FSB combo yields the same clock speed the benchmark results/speeds in PCPBench, 3DBench2 and games are different depending on the FSB used to achieve the speed.

infiniteclouds wrote:

Yeah unfortunately my SS7 board doesn't do 50 FSB. I don't notice L2 motherboard cache on your graph? It did affect speeds on my Pentium MMX -- but it had to be disabled in BIOS, not using the L2D command.

My L2E/L2D state was through the BIOS. IMO, L2 manipulation is essential for truly deep throttling with the P55C.

I'm working on bench-marking the scaling of my current Slot 1 build but it is going to take a while. There are less switches and no L2 cache but still 5 switches that yield different speeds (ICD, BPD, ICD+BPD, L1D and L1D+BPD), combined with 5 different FSB speeds to choose from and a whopping 16 different multipliers - it's incredible. Even when a certain multiplier/FSB combo yields the same clock speed the benchmark results/speeds in PCPBench, 3DBench2 and games are different depending on the FSB used to achieve the speed.

I'm looking at replacing my SE440BX-2 to achieve even deeper throttling and do things like using two floppy drives, but even now with only two FSB speeds and the 14 multiplier settings on my Ezra, the flexibility of C3 chips is pretty crazy.

gdjacobs wrote:

That's my observation, as well. Being able to toggle between 233 and 100 would be even more versatile.

That is a nice graph! It will come in handy. These four lines complement eachother nicely to get a good coverage of SpeedSys values.

infiniteclouds wrote:

Yeah unfortunately my SS7 board doesn't do 50 FSB. I don't notice L2 motherboard cache on your graph? It did affect speeds on my Pentium MMX -- but it had to be disabled in BIOS, not using the L2D command.

Same here, 60MHz is te lowest. But it figures, since I only have two Super Socket 7 ATX boards. 50MHz FSB is easier to find in earlier AT boards. But my ATX boards certainly have their strenghts in other areas.

infiniteclouds wrote:

I'm working on bench-marking the scaling of my current Slot 1 build but it is going to take a while..

That is quite a task indeed. Looking forward to your results whenever they are ready.