Nice!

I'll have to check that out. Does this also work with the standard Pentium and MMX?

I've only tried with the POD so far, but I don't see why not.

From setmul docs:

-Pentium P54C test register "TR12" options. Parameters: BPD - Disable Branch Prediction VPD - Disable V Pipeline L1DX - Disable […]
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-Pentium P54C test register "TR12" options. Parameters:
BPD - Disable Branch Prediction
VPD - Disable V Pipeline
L1DX - Disable L1 cache exclusively
CCD - Disable L1 code cache
DCD - Disable L1 data cache
PFE - Pentium Features Enable; Resets the above TR12 options to default.

Nice to see these Pentium options of SetMul put to good use!
Originally I tested it on a Gold-Capped Pentium 90MHz (P54C): All worked fine. After that I also tried it with one of my Pentium MMX processors, 200 or 233MHz (P55C): The TR12 switches no longer had any effect, as if intel removed these registers... So I am surprised to see it work on the POD 200. POD 200 being an MMX model AFAIK.

Edit: correction - The TR12 settings actually do slow down all six different Pentium MMX processors I have here. i just tested that properly. So AFAIK it just works with any Socket 7 Pentium.
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I wish I could disable the motherboard cache by software 🙁 (even if the restart is kinda fast)
one question, If I set setmul for 500MHz on ms-dos (400 original), and I restart and boot into Windows xp, it's goint to stay at 500MHz or 400MHz?

ibm5155 wrote:

I wish I could disable the motherboard cache by software 🙁 (even if the restart is kinda fast)
one question, If I set setmul for 500MHz on ms-dos (400 original), and I restart and boot into Windows xp, it's goint to stay at 500MHz or 400MHz?

Setmul commands only live during the session they are started, so they would not survive a reboot. I believe the docs say it is not compatible with XP (among other more modern OSes).

A real shame it doesn't work on the MMX. That CPU is just a little bit too fast without caches and could benefit from some further slowing down 🙁

I feel pretty lucky then that it works on my Pentium Overdrive MMX.

Guess the situation is that somewhere along the production of the Pentium MMX they dropped the Test Registers, and it may be interesting to try out some older MMX models to see if they still support the Test Registers.

gerwin wrote:

Nice to see these Pentium options of SetMul put to good use!
Originally I tested it on a Gold-Capped Pentium 90MHz (P54C): All worked fine. After that I also tried it with one of my Pentium MMX processors, 200 or 233MHz (P55C): The TR12 switches no longer had any effect, as if intel removed these registers... So I am surprised to see it work on the POD 200. POD 200 being an MMX model AFAIK.
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Your P90 is a bit faster than mine (8.97) with L1D. If not too much trouble, would you mind adding your results to my compilation?
https://docs.google.com/spreadsheets/d/1fBPxW … #gid=1443406194

Thanks.

Just a tip, between motherboards, memory configurations and BIOS settings there can be quite some variation.

For example I used 16 MB memory (SDRAM) for better compatibility, but that memory was actually EDO and it slowed things down a bit. Memory timings in the BIOS can also have an impact.

So I wouldn't worry too much about a spread in results using the same CPU.

Thanks, Phil. I think it's cool that different platforms can show different characteristics. It says something about the ALI Aladdin V and SDRAM.

Yup.

Your thread brings back good memories.

I looked up some old posts of mine from 2010 when I did my own cache experiments and benchmarks. I actually started off with a Slot 1 system, but quickly found that socket 7 is the way to go.

You definitely paved the way for my inspiration. 😀 Thank you!

Here are all the combinations of setmul switches and how they effect performance on my POD 200MMX:

I'm wondering a bit here, but could such a program possibly be able to enable the motherboard cache in a s7 rig which is running a Tillamook?

Sadly, in retesting my Pentium 120 cpu with the test registers, I found DCD and CCD (data and code cache) have no effect. These two switches are what allow my POD 200MMX to get into 486 levels of performance. VPD and BPD do work, which allow smaller performance drops into P90 and P100 ranges, and disabling L1 gets me down to Am386SX-40. I'm pretty stoked that the POD supports all these TRs, it makes it a very flexible CPU, from 386DX-25->386DX-33->486-16->486-20->486-25->P120->P133->P166->P200.

clueless1 wrote:

Sadly, in retesting my Pentium 120 cpu with the test registers, I found DCD and CCD (data and code cache) have no effect. These two switches are what allow my POD 200MMX to get into 486 levels of performance. VPD and BPD do work, which allow smaller performance drops into P90 and P100 ranges, and disabling L1 gets me down to Am386SX-40. I'm pretty stoked that the POD supports all these TRs, it makes it a very flexible CPU, from 386DX-25->386DX-33->486-16->486-20->486-25->P120->P133->P166->P200.

This might actually be an interesting find. Better go start hoarding those 200MHz MMX Overdrives real quick before this gets verified by the masses 😜.

That is indeed very interesting!

How on earth P200 may degradate to 386-25???

I wonder if 386-25 system from your test have L2 cache or not.