shock__ wrote:Jepael wrote:What's the type of the 4-bit FIFO chips?
74ALS232 (16x 4Bit)
Thanks. Should work. If there exists a "HC" version, it will have more symmetrical output drive for the R2R dac, but I would not worry (the original LPT port had "LS" types as well).
shock__ wrote:Jepael wrote:And, there is no series resistor between FULL output pin and transistor base, it needs one or it might blow up something.
Gonna check into that - just copied that part 1:1 from the board/scheme (which uses a different transistor [H9014])
H9014 is also pretty standard general purpose transistor, so it has no built-in base resistor. Maybe there actually is a resistor as the schematic is more like a block diagram instead of full schematics, or then the ICS chip output is designed to drive a transistor directly, so it is not a regular logic level output. Or they did not care, it would still work but it would not be professional 😀
shock__ wrote:Jepael wrote:I don't see how the samples are clocked out at 7kHz, I see there is C2/R3 combo but it won't oscillate by itself, is there something missing?
Nope, tbh I was kinda puzzled by that part of the schematic as well - just wanted some clearance on that. I guess I'll go with a 555 circuit then.
OK, 555 would work, I can't really suggest a better hobbyist chip for the task. 74xx4060 can be made to generate clock with RC circuit or crystal, and you can also make an RC oscillator if you have few spare logic gates, but 555 is just as good. I think the ICS chip has internal oscillator circuitry, so that there is an external resistor/capacitor combination to set the frequency. The variable trimmer resistor might be used to fine tune the frequency at factory to 7kHz (+/- 5%) as the specs say.
shock__ wrote:Yup, I'm aware of that detection routine, but is the flow control actually used ingame when giving out samples (as in will the software stop sending samples when the FIFO is full or will it keep going and excess samples being dropped at the FIFO)? (if it's done the first way one of the FIFOs could be omited and data passed off to the Covox directly)
Well, like I said, it fills FIFO in timer interrupt until it sees it is full. https://github.com/id-Software/wolf3d/blob/ma … D_SD_A.ASM#L444. As the sampling rate is defined by DSS itself, and if continuous data stream is wanted at max sampling rate, there is little point not to poll the FIFO full signal. The only exception is that you want a sampling rate less than what the DSS does, like 6kHz, then you can just feed one sample in a 6kHz timer interrupt or something like that. But it will skip samples if FIFO is full, so you cannot send it samples in a 8kHz timer interrupt for example, the FIFO will work only when average is the 7kHz generated by DSS, and when you send it 7kHz worth of samples in average, in max 16 sample bursts.