maxtherabbit wrote on 2023-08-04, 12:59:Perhaps they intended it to be a read of port 23h (checking bit 0 of whatever register index was previously selected)?
That could indeed be the case, however in the chipset docs they clearly mention the need for writing to 22h before every access due to the index being reset after every read/write:
SiS wrote:The index is reset after each data access. Every data access to port 23h must be preceded by an index write to port 22h, even if the same register is being accessed.
Then I thought it may be related to Cyrix CPUs, since it uses the same pair of I/O ports as the SiS chipset (22h/23h) for accessing some CPU registers (although a different range of values), and in other sections of the BIOS I noticed that reads of port 22h appeared to be followed by access of some Cyrix configuration control registers. However in the Cyrix 5x86 CPU BIOS Writer's Guide it says that:
Cyrix wrote:Each port-23h data transfer must be preceded by a port-22h register index selection, otherwise the second and later port-23h operations are directed off-chip and produce external I/O cycles. Reads of I/O port 22h are always directed off-chip.
My guess right now is that the AMI BIOS is using port 22h as some undocumented status register (the range of values is probably restricted to avoid conflicts with the registers for both the SiS chipset and Cyrix CPUs). If that's the case, then what would be that last check that is performed to allow setting the Cache Burst Read Cycle to 1T? Well, the answer may be in the datasheet for the slightly older SiS460 chipset, direct ancestor of the SiS471. Here's what it says about reg. 51h:
The attachment SiS460_reg51.jpg is no longer available
Identical to the 471, with the exception that the Cache Burst Read Cycle should only be set to 1 (2T) for 386 CPUs which the 460 supports.
Knowing this, my (very speculative) theory about this is: with the SiS 460 and 471 chipset being so similar in terms of register configuration, this SiS 471 AMI BIOS probably inherited lots of legacy code from older 460 BIOS (the presence of stuff like 80286 or 486SLC/DLC in the table of supported CPUs could also be an indication of copy-pasting code from previous BIOSes by the developers). So, that section that gates the Cache Burst Read Cycle setting behind some checks would be a leftover from an older SiS460 BIOS that went unnoticed during testing (which given the problems with some of the other timing settings would be consistent with subpar QA on AMI's side).